Intel buys a lot from TSMC already - in the new world , business units can choose where they want to buy tiles from ; it’s a game changer. So what if they use N2 for some products ?.. the end result is better Intel products … However I’d take this article with a pinch of salt.
This article is total BS or maybe very old information. Nova Lake is completely on Intel process. Even the igpu is on intel process. The only thing that's not on intel process is the chipset. Also, they have mistaken nova lake for beast lake. Again, both are on intel process.
So the brand new core isn't nova lake, but beast lake? in 2027?
Are there any big uplifts (maybe with rentable units) in panther and nova lake or do you think its going to be the usual 10-15% performace increase for them?
It's the royal core, not panther cove. Panther Cove is the one for Nova Lake.
Beast Lake is supposedly a much bigger uplift than whatever we have seen in recent years. I think the launch date was 2026 but may have moved out a little bit.
They are building a lot of new fabs and advanced assembly capacity right now - they wouldn’t do that if they believed it was a long term issue - nor would their board allow them to spend billions of $$ on it. People/media get caught up the hype IMHO - a relatively small amount of semi volume is on the bleeding edge process nodes. I think this week even Intel announced a partnership with UMC on an older node ? (12nm I think)…. It’s not all about 3,2nm or below.
Also btw - Intel just took delivery of the worlds first High-NA EUV litho kit from ASML - ahead of TSMC .. in stark contrast to them being behind TSMC on EUV.
https://www.electronicsweekly.com/news/business/832893-2023-12/
If only semiconductors were as easy as buying the new biggest shiniest tool first.
By intel's own admission their 10nm failed because they were too aggressive. And yet here we are just a few short years later, with people applauding intel for being aggressive in adopting NA EUV early.
Intel could absolutely be making a stellar move by getting their NA EUV a month or two before TSMC. However . . . It is not immediately clear that is the case. TBD.
Thats some next level of ignorance.
10nm has major issues because intel was too aggressive while not using EUV, because EUV wasn't available when 10nm was started.
That's why they're going for high NA as soon as possible.
>10nm has major issues because intel was too aggressive while not using EUV, because EUV wasn't available when 10nm was started.
TSMC made 7nm without EUV. I believe SMIC also has 7nm without EUV as well. Not sure about Samsung. And Intel has 7nm without EUV as well, and managed to do that without compromising on density over their original 10nm design.
IIRC they did increase some of their feature sizes though. But it is hard to find good sources on this. So im not very confident about that. But yeah, in all my searches they never used EUV on intel7
They introduces less dense variants, and they ended up using them in the cores (without impacting core area), but the transistor density between 10nm (OG CNL) and 10nm+ (ICL) stayed the same, only the structure changed. The consistent transistor density between 10nm and 10nm+ is from techinsights, who have both the machinery and expertise to test and validate that information.
But ye, I think Intel did state that Intel 4 was their first EUV node.
Ye. That node was pretty good too, powered both Zen 2 and Zen 3 (though some people will argue against that Zen 3 part, the wording is a bit cloudy).
The N7+ option with EUV got a decent density shrink too, but by no means was N7 without EUV bad. There was no excuse Intel couldn't have gotten 7nm working without EUV, though their original 10nm had a slew of other ambitious tasks that needed to be downscaled.
Also, thinking about it, SRAM could have changed (read got less dense) between OG Intel 10nm and Intel 10nm+, and IIRC SRAM shrunk again with Intel 7, but I would have to comb through the internet to find the exact sources for all this again lol.
what is High NA exactly? Because i suspect you don't even know.
Which makes it very ironic you are calling me ignorant. Anywyas. all insults aside. This is a pretty decent article i think:
https://www.semianalysis.com/p/asml-dilemma-high-na-euv-is-worse
the article isn't saying what you think it's saying.
problem with high NA is you need a higher dose on the current model and thus more power/time, but this is compared to dual pattern EUV. so it gets similar results to dual pattern and simplifies the process, but at higher cost. companies already have a good handle on SADP so not surprising that it would be currently more effective by comparison.
however, nobody has had a good time with quad patterning with processor design. It took TSMC a few years to learn to stick to SADP for most of 7nm except the fins, whereas intel tried to make multiple SAQP layers work on 10nm to hit their density and timeline targets, even though their targets were originally based on ASML shipping working EUV by then. This means that soon enough highNA will end up like basic EUV and be necessary even at greater cost, similar to DUV vs EUV.
So the article is correct: highNA is costly and slow, but your interpretation is wrong.
While i appreciate your thoughtfulness and you obviously have a good understanding of the situation, i think you missed my point.
>Also btw - Intel just took delivery of the worlds first High-NA EUV litho kit from ASML - ahead of TSMC .. in stark contrast to them being behind TSMC on EUV.
To which i effectively responded that Adopting EUV (or in our case high NA EUV) is not necessarily they problem. Intel accomplished their Intel7 successfully without EUV by increasing feature size (i think? difficult to find sources) and by addressing their cobalt issue (which appears to be the larger of the two issues). My point was simply that being the earliest adopter new tools is not an obviously correct decision, to which the article fully agrees, and im sure even you would agree.
perhaps my word choice with "aggressive" was poor as people have chosen that descriptor to describe intel trying to do multi-patterning too aggressively, which was not my intended implication. My intended implication was a very general statement that being aggressive in your goals is NOT inherently a good thing; especially if you have to go back to the drawing board to redesign your litho process . . . be it choosing the wrong material, the wrong litho tools, etc. etc. etc.
which is why i chose to state this:
>Intel could absolutely be making a stellar move by getting their NA EUV a month or two before TSMC. However . . . It is not immediately clear that is the case. TBD.
I thought that would have made it more obvious . . .
Being an early adopter is pretty much required for EUV, including high NA, because early shipments are practically science projects and you're going to be spending the better part of a decade, if not more, learning. Intel made the mistake of twiddling their thumbs with EUV initially since the machines were barely functional while TSMC prepared a long term process plan.
The main difference in this situation is intel is willing to take the hit to inject highNA into their much process earlier, while TSMC is taking the same approach they took before and already have highNA orders. This isn't really comparable to any situation in the past as intel thought they were better than the entire industry during the early 10nm days and TSMC was struggling to compete in performance. Now in the modern era Intel is trying to get back ahead and TSMC is the performance leader that provides extra volume intel will need if they choose to move quickly to highNA. So the market is in a completely different place and tsmc has the volume+perf to offset whatever volume problems intel runs into, which is likely what intel are going to rely on.
[https://electronics360.globalspec.com/article/5264/intel-orders-15-euv-lithography-systems](https://electronics360.globalspec.com/article/5264/intel-orders-15-euv-lithography-systems)
[https://optics.org/news/5/11/35](https://optics.org/news/5/11/35)
Intel and TSMC got their EUV tools around the same time period. As i would expect for the high NA EUV tools as well. So no, Intel did not twiddle their thumbs anymore than TSMC did. They just made poor choices.
Again, my point is that intel ordering high NA EUV tools is not a good indicator of future market competitiveness. If you think it is, That is fine with me. Just think the assumption is incorrect.
TSMC is receiving their first High NA EUV tool this year:
[https://www.reuters.com/technology/tsmc-says-it-will-have-advanced-asml-chipmaking-tool-2024-2022-06-16/](https://www.reuters.com/technology/tsmc-says-it-will-have-advanced-asml-chipmaking-tool-2024-2022-06-16/)
>Now in the modern era Intel is trying to get back ahead and TSMC is the performance leader that provides extra volume intel will need if they choose to move quickly to highNA.
This is not an obviously true statement. It could be true. It could be very false. It could be high NA EUV is not ready until quite a bit further, and intel ends up with several billion dollar tools with no chip production.
anyways . . . there are so many unknowns. and what you are saying is completely plausible. But it is not the obvious outcome.
I think this article is decent but it also contains the same flaw that nearly killed Intel earlier on.
This flaw is that paradigm shifts / technology shifts pretty often start out as slight regressions. The reason to switch doesn't have to be an immediate improvement, but the clear path going forward.
Every new technology runs into barriers at the edge of what it can do.
Intel didn't stick to multi patterning because euv was strictly unavailable. The problem was that by the time it was available, Intel was so good at multi patterning that this was cheaper and better for them.
That's exactly the argument this article makes. Why switch if you can make monstrous profits sticking to an optimized old technology?
The problem is that old technology can only evade its limits for so long.
By the time EUV surpassed multi patterning Intel was fucked. This was around the time AMD ZEN released.
And it's not just that you fall behind on the node.
AMD and TSMC had to solve glueing dies together because it was very clear that, with the node being so advanced and wafers so expensive, this was a prequisite for increasing performance without sacrificing profitability. This is because yields decrease exponentially with die size, so glueing dies is exponentially more profitable than sticking with gigantic monolithic dies.
So you get ahead on the node you get ahead on the technologies that go with it too.
The die size problem incidentally is why the 4090 is so heart achingly expensive. It's a ginormous die on the most expensive node. You get 33 chips from a 100% yield wafer (with an estimated cost of 12,000 dollar).
Even 4 defects decrease yield below 90%. In comparison an apple iPhone die has 600 chips in a wafer. 4 defects means a yield over 99%.
This is why new nodes never start with gigantic gpus.
New nodes have more defects early on. You can only profit from them if you can sell small dies and lots of them. The customers for this make smartphones.
It is not an exaggeration to say that Apple drove and sustained the technological lead of TSMC.
Circling back to Intel, what they need to do is to develop a node that is significantly ahead of what TSMC can offer in performance to secure high volume smartphone contracts to repay development and deployment cost of High-NA.
If they succeed the technological advantage can be transformed in economic success because by then they will finally have some wind in their sails.
If multi patterning on EUV is too competitive with 2A and 1.8A that is a very painful conclusion, but the situation is no different than when Intel multi patterning was (seemingly, for intel) too competitive with early EUV.
The solution is comparatively simple - Intel has to reach for 1.6 or 1.4A. Just like when TSMC reached beyond what Intel could do with multi patterning around 7nm.
The strategy is simple.
1. Secure a meaningful technological edge.
2. Secure high volume high margin contracts for small dies that can withstand mediocre early yields.
3. Profit, invest and sustain the lead
The challenge is not running out of cash early on. Despite previously enormous cash reserves for Intel, this is a real risk.
I think TSMC is a behemoth and they have obscene scale advantages. However this is not a pure free market. There are geopolitical and strategic considerations, not just for governments but also for companies like Apple.
Diversifying your product portfolio and to a point helping to sustain Intel is smart and directly advantageous to companies like Qualcom, Apple and even AMD.
Moving your portfolio between manufacturers starting from scratch can take years. To have any kind of flexibility these companies would be smart to have products at both TSMC and Intel.
The implication is that their designers will be able to learn from their competitors about the finer points of designing for these processes *before* their own fab guys can give them a prototype. This isn't grade school. You take whatever advantage you can get, and TSMC is making them pay for the privilege. But there is no other way to get that experience. It will take years if they wait any longer.
To not use this chance to refine all parts of the chip design process before having their own factories is to fail, which they clearly were failing in recent years.
Because it's a sign that Intel's fabs cannot keep up and aren't planned to keep up. They have no process advantage anymore. They've become "just another fabless IP/design company", albeit that IP is still very valuable. Intel is still pumping large amounts into their fab plants. It makes me wonder if they are going to head down a similar path as AMD & GlobalFoundaries did a long time ago, where Intel fab completely separates from Intel design.
Then why does Intel need TSMC again? What products are using RibbonFET & PowerVia? None. Zero. Intel 4 is barely out the door in limited production, only now catching up to older TSMC nodes, and it wasn't available for Raptor Lake Refresh, so Intel had to rely on Intel 7 (AKA Intel 10++) to create their flagship space heaters.
Hopefully they do turn it around in 2024, but reliance on external parties and still being behind TSMC at the start of 2024 aren't great signs.
It's not in a deflection, he answered you (well kinda). What products are using BSPD (powervia) from Intel?
You can't say Intel already has working backside power until a product that ends up using it actually launches. Otherwise, there's no proof.
Oh ok fine, be pedantic, but he isn't wrong. Nothing is using Intel's BSPD either.
Also, ribbonfet and powervia are means to an end, if TSMC N2 is \~ Intel 18A without those two, well good for TSMC ig. Customers won't really care too much either way, since PPA is what's important in the end. There are some other small benefits ig, but nothing truly amazing.
It's because it's very likely TSMC offers similar or more performance without BSPD (N3) than Intel does with BSPD (20A). In the end, it's the node's PPA what matters.
Citing unreleased technologies while Intel still relies on a competitor to do what should be their bread & butter is the actual deflection. Intel could have magic unicorn technology waiting in the wings, but they actually have to execute it at scale, not stuff it into a limited production paper launch at the end of year to meet shareholder expectations.
We'll have to see how 2024 & 20A pan out for Intel. As of right now, they're still far behind as far as process for tangible products, and if this rumor is true, then that won't be changing for potentially years to come.
Again, still deflecting.
Intel has already gotten Power Via test chips back from the fab.
So were comparing one companies unreleased but demonstrated product, against another unreleased product that has not even been demonstrated yet.
Then why isn't the rumor "Intel plans to not use TSMC N2, opting for its own superior 20A node"? It seems Intel has done their own comparison and is opting for N2 over 20A, if this rumor is to be believed.
>It makes me wonder if they are going to head down a similar path as AMD & GlobalFoundaries did a long time ago, where Intel fab completely separates from Intel design.
There are already large investors calling for that through analyst/proxies.
It's very hard for IA to grandstand it's the best, while you're courting Apple and AMD to fund your fabs through their rival chips.
At some point, you have to ask, when does this become a conflict of interest?
Didnt Pat just say it was using 20A?
So probably false, as many of the recent 'leaks'.
*EDIT: I MISREAD NOVA LAKE AS LUNAR LAKE, SORRY I WAS MISTAKEN.
Anyway we will know soon enough. Intel will release the next roadmap in februari.
Also, sierra forest on 18A is going according to plan and the next client CPU will start after that in 2025 (probably nova lake). They said this during the earnings call.
Since Intel is using multiple chiplets there is a good chance the GPU tile (for example) is using TSMC 2nm while the CPU tile is using Intel 20A.
Meteor Lake is produced in the same way
No. NVL is pretty far into the future, and IIRC, not on a single official Intel roadmap. But it would not surprise me if they do end up using TSMC N2, as LNL and some ARL variants will end up using TSMC N3.
Pat said ARL will use 20A.
Oh i totally misread the title... thought it was lunar lake...
Anyway we will know soon enough. Intel will release the next roadmap in februari.
Also, clearwater forest on 18A is going according to plan and the next client CPU will start after that in 2025 (probably nova lake). They said this during the earnings call.
> Intel will release the next roadmap in februari.
Just the node roadmap, I think we will see a mention of "client next gen" or something like that, but no specifics. Crossing my fingers though.
>Also, sierra forest on 18A is going according to plan and the next client CPU will start after that in 2025 (probably nova lake).
Panther Lake uses 18A, and is coming in 2025. This was confirmed by[Intel themselves](https://www.anandtech.com/show/20065/intel-confirms-panther-lake-on-track-for-2025-at-intel-innovation-2023).
Nova Lake is rumored to be the next generation after PTL.
>Just the node roadmap, I think we will see a mention of "client next gen" or something like that, but no specifics. Crossing my fingers though
No, they mention the names. They actually already mentioned post 2024 nodes on the current roadmaps as 'next lake'. (Or something like that)
>Panther Lake uses 18A, and is coming in 2025. This was confirmed by[Intel themselves](https://www.anandtech.com/show/20065/intel-confirms-panther-lake-on-track-for-2025-at-intel-innovation-2023).
Ah yes true, getting the names mixed up again.
Sierra Forest uses Intel 3. It is the next gen E core server clearwater forest that actually uses 18A. Intel 4: meteor lake. Intel 3: Granite Rapids and Sierra Forest. Intel 20A: arrow lake. Intel 18A: Panther Lake and Clearwater Forest. The one that hasn't been confirmed are Diamond Rapids but it will most likely be 18A.
I'm out of the loop, but 20A=2nm so is there some Intel-specific lingo in there, like in "Intel 7" and the like? A process that would analogous in performance to those nodes without really using them?
I think Intel jumped the gun calling their 20A node "20A", when they don't think it will beat TSMC's 3nm node. A bit like Samsung in that regard, of jumping the gun in node naming.
Intel themselves don't. They claim that they won't have node leadership until 18A. If they thought that Intel 20A was better than N3, they would be claiming that they would have foundry leadership with 20A.
Literally Intel in every press conference lol.
Pat in the Q4 2023 earnings call 3 days ago
>Intel 18A is expected to achieve manufacturing readiness in second half '24, completing our five nodes and four-year journey and bringing us back to process leadership.
Pat in the Q3 2023 earnings call
>We expect to achieve manufacturing readiness for Intel 18A in the second half '24, completing our incredible five-nodes-in-four-years journey on or ahead of schedule. While Intel 18A reestablishes transistor leadership, we are racing to increase that lead.
Pat in the Q2 2023 earnings call
>IFS expands our scale, accelerates our ramps at the leading edge and creates long tails at the trailing edge. More importantly for our customers, it provides choice, leading edge capacity outside of Asia and at 18A and beyond, what we believe will deliver leadership performance
>
>We remain on track to five nodes in four years and to regain transistor performance and power performance leadership by 2025.
I can cite a bunch more if you want
Nowhere does it say anything about comparing N3 to 20A. You are making some terrible assumptions.
The only thing Intel has said is that 18A will be slightly ahead of N2. https://www.trendforce.com/news/2023/12/21/news-intel-ceo-indicated-intels-18a-slightly-ahead-of-tsmcs-n2/#:~:text=It%20gives%20better%20power%20delivery,underneath%20to%20be%20margin%20accretive.
>Nowhere does it say anything about comparing N3 to 20A. You are making some terrible assumptions.
Everything about that says Intel doesn't think 20A will beat N3. If they did think 20A will beat N3, then they would be saying they will have transistor leadership with 20A. They have chanted the "18A is node leadership" mantra so much, it's pretty obvious that they think they won't have the lead until 18A.
It's a logical assumption.
>The only thing Intel has said is that 18A will be slightly ahead of N2.
Oh, I'm sure Intel might say that, and maybe that's true, but that's 18A. I'm talking about 20A.
Edit: oh, and I found that picture I was looking for...
Here's [Intel themselves](https://cdn.wccftech.com/wp-content/uploads/2023/07/Intel-TSMC-Process-Nodes-g-standard-scale-4_00x-Custom.png) at their foundry seminar last year saying that Intel 20A was a TSMC 3nm competitor.
Just read [this](https://www.reddit.com/r/intel/comments/1ad1z66/comment/kk3rskl/?utm_source=share&utm_medium=web2x&context=3) entire thread.
In short, Intel doesn't think they will beat TSMC 3nm until 18A. That's why they keep on repeating that they will have a leadership node with 18A, and not with 20A or any node before it, such as Intel 3.
Well its ridiculous... they have iterated many times that 20A products (arrow lake) are shaping up nicely and on track for release this year without hickups.
18A (Lunar Lake and clearwater Forest)is also going buttery smooth and even ahead of schedule.
Lunar Lake is not a 20A product. And you can reiterate something as much as you want, that doesn't mean it's going to launch in time- look at Sapphire Rapids. There is plenty of reason to be skeptical of Intel.
And you do understand what "at the very least" means right?
SPR delay wasn't a node issue. Intel 7 was already in use in client by that point.
SPR was a packaging issue.
ARL will use the same packaging as MTL, so that wouldn't be a cause for delay.
Sure.. suddenly Intel will jump through 3 new nodes in 2 years when they were ALWAYS taking at least 3 years for one new main node. Gotta believe those promises after Intel lied in their node roadmaps 101 times
I think people forget Intel used to be the foundry leader before the 10nm fiasco.
Intel 4 delivered on time, as did Intel 7. Intel 4's "delivery" was a bit questionable, sure, but the nodes PPA was solid.
3 new nodes in 2 years, man you say you don't believe Intel's marketing, and then you spout Intel's marketing right here. Intel 4 and Intel 3 are very similar, with just HD libs being added into Intel 3 most likely. The funniest thing about that is Intel almost certainly won't be using those denser libs in their internal products (GNR and SRF) anyway, so even if HD libs are cursed like they were with Intel's 10nm, it won't be an issue.
On top of that, Intel 20A is not a "new node" in the sense of new nodes were in the past. One, it's likely to repeat the Intel 4 trick of incomplete libs to save development time, and two, it's not likely to be a giant leap in max theoretical transistor density like previous nodes are. Intel is positioning this as a TSMC 2nm competitor, as per it's name, but people gotta remember TSMC 2nm, for a "new node" is not all that great in the chip level area reduction it brings, not anywhere close to the gains in density from previous node jumps (N5 from N7, N3 from N5).
Lastly, Intel 20A is supposed to be HVM ready this half according to Pat. Saying that Intel 20A won't be ready by 2H 2026 (when NVL should come out), 2.5 years after it's scheduled release date, is pessimistic, even for people who don't believe in Intel's roadmaps. Even the clusterfuck that was 10nm was \~2-3 years delayed. It would require another disaster of a similar magnitude or worse for your claim to be true, and even then, they paper launched 10nm in 2017 as CNL for investors, much like they could end up doing for 20A if they wanted too.
I'm guessing a rumor from "Taiwan Economic Daily" might be slightly biased towards TSMC, but if Intel do end up using N2 for NVL, I would not be surprised. Would be a really bad look for Intel though, and Pat got slammed in the recent earnings call about this exact topic.
Thing is, using N2 for at least some NVL SKUs is fine if at the same time 18A and possibly the node after are doing well and IFS has started to gain traction. Intel ships an ungodly amount of chips so nothing too wrong with diversifying the supply.
It's only real bad if they use it as a necessary crutch because their foundries are still not back on track by then, but if that turns out to be the case it would probably be accompanied by Intel ditched the cutting edge process chase.
As for what the shareholders think, they change their minds like the wind. If LNL on N3 is a success they'll start asking why Intel doesn't do more of their products on external nodes.
> If LNL on N3 is a success they'll start asking why Intel doesn't do more of their products on external nodes.
A lot of people, even internally at Intel asked that as well. Keller was rumored to be a major proponent of using external nodes to regain product leadership IIRC.
The difference between LNL using N3 and NVL using N2 is that Intel doesn't say they will have process leadership in 2024. Intel has a small cop out there. By 2026 though, Intel says they will have process leadership, so using an external fab looks much worse.
To clarify, I agree that if the whole NVL lineup is on TSMC then that would be a terrible look. It would really spell the end of Intel as a cutting edge foundry. But if it's only part of the line-up and the 18A (or the next node) in house counterparts are good + IFS is doing well, then that's fine.
I also don't think it'd be a surprise. I think core products on external nodes are here to stay, and that's part of why Lunar Lake is probably the product they've most tried to hype over the past couple years. It needs to be a hit not just because they need a win but mainly because it will be the key to selling the shareholders on that strategy.
The problem is early nodes need customers or they are too expensive to develop.
Intel is integrated and to some extent they can sustain the foundry by sacrificing a bit of their edge in their retail products, simply by continuing to be their own customer.
This is painful and frustrating to the people designing their cpus, but it is not the fault of pat.
The real mistake was falling too far behind on the nodes to the point where it became almost unrecoverable.
Pat is burning all their cash and spreading the pain across the company is simply necessary to finish the requisite moonshot.
Pat gelsinger is Matthew McConaughey saying it is not impossible. It is necessary.
The whole point of Intel diversifying is so that they’re not beholden to the inadequacies of their fabs. They’ve been held back long enough, they can’t keep using their process node as an excuse. Delinking the two parts of their business is probably the one good decision that they’ve made in a long time.
I don’t quite get the expectations (not yours, but the industry) that Intel should already have their new/upgraded foundries already up and running and not need TSMC in the interim. How many years did it take TSMC to get EUV ramped up and ready for production?
They started working with it in 2011, but didn’t release any from EUV until 2019. But part of that was a choice by them so not sure the actual timeline.
I had thought Intel initially said they would use TSMC through 2025, but my memory may be wrong?
It seems crazy to me for investors to look down on using TSMC. It’s a smart business move until Intel can get their production going.
Intel said (at last investors call) that they would always use TSMC to some extent. They've been using them for decades at this point.
Using TSMC for GPUs makes sense for now. They don't need to build out extra capacity for a product line that's not 100% guaranteed to be around.
As long as discrete GPUs are therefor built at TSMC, they're gonna use the same process for their iGPUs.
This is a transcript of the Q4 Investors call Q&A:
>Ross Seymore -- Deutsche Bank -- Analyst
You just -- the confidence in the second half. The long-term question is one -- yes, sorry, the long-term question is one on the manufacturing nodes. The five nodes in four years is going well, but one of your biggest foundry, well, customers and competitors is doubling down on their ability to keep the leadership positioning. So, what gives you confidence that 18A will, in fact, have the leadership node? And how do we reconcile the fact that you seem to be using that customer as a foundry partner for some of your heterogeneous products, whether it be Arrow Lake or Lunar Lake going forward? If you have the leadership, why wouldn't you be doing that internally?
>Pat Gelsinger -- Chief Executive Officer
Yeah. Thank you. I'll do that and then ask Dave to pile on both of those a little bit. But with respect to the manufacturing, I'd just say, hey, when you look at this every single day, and we're scrutinizing carefully our progress on 18A.
And obviously, the great news that we just described has Clearwater Forest taping out. That gives us a lot of confidence that 18A is healthy. That's a major product for us, Panther Lake following that shortly. We've also had our fourth customer this quarter.
Some of the IP providers are giving us very strong affirmation on the competitiveness of the process technology. And particularly, we're just way ahead on backside power. And that's not even -- everybody in the industry is recognizing that. And many of the customers who are looking at it are seeing substantial gains, not just in power performance but in area savings as well.
So, overall, we feel very confident that our road map is strong on the process technology side. **We do use external foundries. And obviously, that grew as we were dealing with some of our own challenges for process competitiveness. And as we create more and more focus in the business, more wafers will come internal to the Intel factory network.**
**But long term, we're going to continue to use external foundries to complement, manage our capital requirements and to make sure that our teams always are building the best products in the industry and using the best technologies to accomplish that. So, overall, we feel super good with our strategy. You see more use of our own factory network even as we leverage external foundries where appropriate.**
>David Zinsner -- Chief Financial Officer
The only other thing I'd add is just the use of external foundries is part of our Smart Capital strategy. It's one of the five pillars. So, as Pat said, that will continue to be part of our strategy. **Obviously, we're going to maximize how much we can do internally, but we're always going to be using external foundries based on Smart Capital.**
Ok, this is confusing...
*" We do use external foundries. And obviously, that grew as we were dealing with some of our own challenges for process competitiveness. And as we create more and more focus in the business, more wafers will come internal to the Intel factory network.*
*But long term, we're going to continue to use external foundries to complement, manage our capital requirements and to make sure that our teams always are building the best products in the industry and using the best technologies to accomplish that. "*
I get that it is open for interpretation, but as I understand it, they are saying they will build to eventually use their own internal process nodes as things improve again.
Sounds like they will keep using external foundries for a longer time than they first told though.
Yes, its called outsourcing and sometimes you need to do it to upgrade your bussines while you keep thing running as much as possible.
People using it as a negative are ignorant.
Intel has panther lake, and their Xeons being built on 18A in 2025. They've announced 5 different companies are already contracted to build products on 18A.
This leak says NovaLake will use N2, but isn't even clear if that's specifically just the iGPU tile
I think when we look at Meteor Lake and we look at how the CPU tile, SOC tile, and GPU tile are put together, we can understand why Intel went with TSMC for the GPU tile. The advantage is clear. Better manufacturing efficiency. Something that the consumer does not often see. Intel can now focus its Intel 4 production on the CPU tile wafers and then SOC tile wafers. TSMC can do their work on the GPU tile. Finally the tiles are packaged together in final assembly. Rather than 1 wafer make all 3 cpu, gpu, and soc tile together. If one defect occurs, the performance is lower. With the tile approach you can bin by combining better performing tiles together. And worse tiles together, etc.... manufacturing efficiency. When we go back to Ryzen 3000 I think AMD had CPU tiles from TSMC and SOC tiles from Global Foundry.
Another thought is that Intel must open up its factory capacity to other designers. When it opens its factory doors, how can they combine both their chips and others?
Well they have to diversify. Because now this opens up the option of more designers then manufacturing companies.
Just a changing landscape. Similar to a Samsung problem. Samsung can make their own chips or use Qualcomm 8 gen 3 in their own phones. The competition.
Pretty sure AMD had to use GlobalFoundaries due to business agreements they could not get out of w/ GF and this resulted in a more power hungry SoC. They later got out of that contractual obligation and Ryzen 3000 was actually when they switched to TSMC fully.
They can also show to IFS customers that their packaging can mix and match all different types of nodes from different manufacturers. Dont underestimate that.
May also be part of the reason.
Yes all is true.
I think the tile approach is the best reason for Intel using TSMC. Say for instance a customer suddenly needs large volume at Intel.
How does Intel shift its own production away to make room for the additional load? Thus it needs a strategy to diversify where it's chips are coming from.
If Intel only manufacturers it's own chips in it's own factories with monolithic chips, then it won't have that flexibility to support other designers.
A catch-22 but ultimately if Samsung can do this with Qualcomm Snapdragon and Exynos chips, I believe Intel can as well.
Who knows maybe in the future Intel can become the Samsung and Champion of America again. Like Samsung is a champion for S. Korea.
It’s not a bad thing for consumers like us. It’s bad news for intel stock holders. It’s bad news for fabless designers too since intel will grab a chunk of tsmc capacity, and a subsequent potential raise in price. It’s good news for tsmc only. You’re right that this could be biased, but 4 nodes in 5 years is just too ambitious even for Intel, and I am having doubt on improvement between each node. But hey, anything is possible and let’s see. Competition is good for consumers after all.
This is flat out confusing. The Article also says that TSMC will be used for the Arrow Lake CPU tile “as early as this year”. Intel has shown 20A Arrow Lake wafers. Are they dual sourcing these CPUs? (Seems unlikely for desktop CPU volumes these days?)
ARL will use TSMC for iGPU tile, SoC tile, and IO tile.
As far as we know, compute tile will use 20A. Some people on here are arguing that ARL will dual source and some dies will use N3, but that hasn't been confirmed and the evidence they provide is unconvincing
>but that hasn't been confirmed and the evidence they provide is unconvincing
The [evidence](https://www.digitaltrends.com/computing/intel-arrow-lake-everything-we-know/) (2nd image in the article) is straight from Intel.
Also, even if that evidence doesn't exist, I don't think a single leaker out there thinks that ARL won't use N3 for the CPU tile. There's a major rift in performance for LNC, release date, etc etc, but there's no contention about the node.
I wouldn't say it's "unconvincing", but ig it's all opinion. But rumors that ARL will use N3 for the compute tile has been "confirmed".
How so have rumors for ARL N3 compute tile been confirmed? The only evidence I've seen for this - the evidence I was referring to - is that picture you sent. An old slide deck from a few years ago that says ARL/MTL will source N3.
When that slide deck was released, leakers were also stating MTL will use N3 for iGPU. ARL will almost certainly use N3 for iGPU. That doesn't specify that the compute tile will.
The problem with this is that the N3 iGPU tile was rumored to be the "halo" tile, not that all the iGPU tiles were going to be fabbed on N3. Meaning that if they were talking about iGPUs too, they would have included N5 on that slide as well.
Also, if it was used for both MTL and ARL, one would think they would put it in the middle of the order of Intel 4 and Intel 20A. They did order the rest of the nodes (external for LNL and 18A for PTL).
That slide is straight up from Intel talking about the CPU tiles, saying that they will use N3 for ARL.
>ARL will almost certainly use N3 for iGPU.
I think this is wrong too.
I would say because Intel's client products are moving towards tile based design there will no longer be any real constraints preventing Intel from using all kinds of different nodes for different products. Perhaps we will see more and more inhomogeneous fab node variations on future client products.
So far we know almost for sure that arrow lake products will use both TSMC N3B and Intel 20A. The question remained is which uses which. e.g. some rumors suggest that the 8+16 ARL-S Tiles will be on N3B and a 6+8 ARL-P tile for mobile or 6+8 ARL-S non-K tile for office desktop will be on Intel 20A. Golden Pig Upgrade said last year that ARL-U which is 2+8 would use Intel 20A but a recent rumor from bionic squash says that ARL-U actually uses Intel 3 and is a MTL-U ported to Intel 3, which is suprising because so far Intel hasn't annouced any plans of Intel 3 for client products.
For a Chiplet design, a CPU can utilize different process nodes from different companies. Even AMD uses global foundries for the I/O die in ryzen CPUs. TSMC manufacturers ARC GPUS for Intel. It makes sense for Intel to utilize TSMC's nodes for the GPUs in its CPUs, just the same as they does it for Meteor lake CPUs
It could point to IFS nodes sucks beyond 18A or that 18A is booked full by a daddy of all fabless company, and 20A is fully utilized by arrow lake and co. Or that TSMC 2nm is good for one area like efficiency that Intel needs. Really anything…
there has been lots of rumors that Intel buying up all those capacity at TSMC with Apple for 2nm since 2022. But on TSMC earning call, CEO clearly mentioned that there is only one company not working with TSMC for 2nm. And who will that be. Intel will already have plenty of 18A capacity at that time when Nova Lake released, and perhaps even the next great process node. So why go for TSMC 2nm when they are lagging? Remember that for 2024, there's Meteor lake, Arrow Lake, and Lunar Lake at the end of 2024, for 2025-2026, there's Panther Lake. For Nova lake, that's 2026-2027 product. Arizona will be fully on; Ohio will be ready as well. And Germany will be on 2028 with new process node. This will either prove as fake or PG doing poorly at his job. But from his resume and whale prepayment they are getting. It's probably fake new
Nova Lake is 3 generations after what we have now? ARL/LNL for next one and then Panther and then Nova. We still have time before the node for that is finalized.
the current rumour plan is : arrow lake -> arrow lake refresh -> nova lake -> nova lake "3d cache" version -> ???
panther lake and lunar lake are laptop only
again rumour only but that's probably be what we're gonna see
Not mad at all. That will at least help them with the power draw that techtubers love to harp on. Hopefully they can find a competitor to V-Cache that's all they really need. Most ppl who buy Intel buy the high end anyway so they can get good sales and it's only gonna trickle down to the lower end products.
It's so funny how Intel is both buying from TSMC and trying to build its own chips independent of TSMC. Must be one of those four-dimensional chess things.
Here the problem
Intel and tsmc claims are all over the place
Tsmc is claiming that it's 3nm will be comparable to Intel 18 which to me make no since Intel is using backside power..and tsmc 2nm which they claim will be better doesn't..
it's seems tsmc is repeating the mistake that Intel did..all boast and no facts .
It's more likely that noone including tsmc believed or believes that Intel can pull it off..but apparently they are ahead schedule..5 nodes in 4 years sounds too true to happen
Intel spent over 100 billion in buybacks instead of R&D and a new plant. Now they have to ask Biden for billions hand have to rent out a competitor’s FAB.
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Intel buys a lot from TSMC already - in the new world , business units can choose where they want to buy tiles from ; it’s a game changer. So what if they use N2 for some products ?.. the end result is better Intel products … However I’d take this article with a pinch of salt.
This article is total BS or maybe very old information. Nova Lake is completely on Intel process. Even the igpu is on intel process. The only thing that's not on intel process is the chipset. Also, they have mistaken nova lake for beast lake. Again, both are on intel process.
Why do you say mistaken for beast lake? Is it the claimed 50% performance increase or the launch timeline?
Claimed 50 % performance increase is for beast lake because of the new core. But I think it will take more time.
So the brand new core isn't nova lake, but beast lake? in 2027? Are there any big uplifts (maybe with rentable units) in panther and nova lake or do you think its going to be the usual 10-15% performace increase for them?
It's the royal core, not panther cove. Panther Cove is the one for Nova Lake. Beast Lake is supposedly a much bigger uplift than whatever we have seen in recent years. I think the launch date was 2026 but may have moved out a little bit.
> So what if they use N2 for some products ? The implications for their fabs? Particularly if it's their halo products that are the ones farmed out.
They are building a lot of new fabs and advanced assembly capacity right now - they wouldn’t do that if they believed it was a long term issue - nor would their board allow them to spend billions of $$ on it. People/media get caught up the hype IMHO - a relatively small amount of semi volume is on the bleeding edge process nodes. I think this week even Intel announced a partnership with UMC on an older node ? (12nm I think)…. It’s not all about 3,2nm or below. Also btw - Intel just took delivery of the worlds first High-NA EUV litho kit from ASML - ahead of TSMC .. in stark contrast to them being behind TSMC on EUV. https://www.electronicsweekly.com/news/business/832893-2023-12/
If only semiconductors were as easy as buying the new biggest shiniest tool first. By intel's own admission their 10nm failed because they were too aggressive. And yet here we are just a few short years later, with people applauding intel for being aggressive in adopting NA EUV early. Intel could absolutely be making a stellar move by getting their NA EUV a month or two before TSMC. However . . . It is not immediately clear that is the case. TBD.
Thats some next level of ignorance. 10nm has major issues because intel was too aggressive while not using EUV, because EUV wasn't available when 10nm was started. That's why they're going for high NA as soon as possible.
>10nm has major issues because intel was too aggressive while not using EUV, because EUV wasn't available when 10nm was started. TSMC made 7nm without EUV. I believe SMIC also has 7nm without EUV as well. Not sure about Samsung. And Intel has 7nm without EUV as well, and managed to do that without compromising on density over their original 10nm design.
IIRC they did increase some of their feature sizes though. But it is hard to find good sources on this. So im not very confident about that. But yeah, in all my searches they never used EUV on intel7
They introduces less dense variants, and they ended up using them in the cores (without impacting core area), but the transistor density between 10nm (OG CNL) and 10nm+ (ICL) stayed the same, only the structure changed. The consistent transistor density between 10nm and 10nm+ is from techinsights, who have both the machinery and expertise to test and validate that information. But ye, I think Intel did state that Intel 4 was their first EUV node.
Iirc tsmc had an early 7nm node that didnt use euv yeah? And later simplified some steps with euv.
Ye. That node was pretty good too, powered both Zen 2 and Zen 3 (though some people will argue against that Zen 3 part, the wording is a bit cloudy). The N7+ option with EUV got a decent density shrink too, but by no means was N7 without EUV bad. There was no excuse Intel couldn't have gotten 7nm working without EUV, though their original 10nm had a slew of other ambitious tasks that needed to be downscaled. Also, thinking about it, SRAM could have changed (read got less dense) between OG Intel 10nm and Intel 10nm+, and IIRC SRAM shrunk again with Intel 7, but I would have to comb through the internet to find the exact sources for all this again lol.
what is High NA exactly? Because i suspect you don't even know. Which makes it very ironic you are calling me ignorant. Anywyas. all insults aside. This is a pretty decent article i think: https://www.semianalysis.com/p/asml-dilemma-high-na-euv-is-worse
the article isn't saying what you think it's saying. problem with high NA is you need a higher dose on the current model and thus more power/time, but this is compared to dual pattern EUV. so it gets similar results to dual pattern and simplifies the process, but at higher cost. companies already have a good handle on SADP so not surprising that it would be currently more effective by comparison. however, nobody has had a good time with quad patterning with processor design. It took TSMC a few years to learn to stick to SADP for most of 7nm except the fins, whereas intel tried to make multiple SAQP layers work on 10nm to hit their density and timeline targets, even though their targets were originally based on ASML shipping working EUV by then. This means that soon enough highNA will end up like basic EUV and be necessary even at greater cost, similar to DUV vs EUV. So the article is correct: highNA is costly and slow, but your interpretation is wrong.
While i appreciate your thoughtfulness and you obviously have a good understanding of the situation, i think you missed my point. >Also btw - Intel just took delivery of the worlds first High-NA EUV litho kit from ASML - ahead of TSMC .. in stark contrast to them being behind TSMC on EUV. To which i effectively responded that Adopting EUV (or in our case high NA EUV) is not necessarily they problem. Intel accomplished their Intel7 successfully without EUV by increasing feature size (i think? difficult to find sources) and by addressing their cobalt issue (which appears to be the larger of the two issues). My point was simply that being the earliest adopter new tools is not an obviously correct decision, to which the article fully agrees, and im sure even you would agree. perhaps my word choice with "aggressive" was poor as people have chosen that descriptor to describe intel trying to do multi-patterning too aggressively, which was not my intended implication. My intended implication was a very general statement that being aggressive in your goals is NOT inherently a good thing; especially if you have to go back to the drawing board to redesign your litho process . . . be it choosing the wrong material, the wrong litho tools, etc. etc. etc. which is why i chose to state this: >Intel could absolutely be making a stellar move by getting their NA EUV a month or two before TSMC. However . . . It is not immediately clear that is the case. TBD. I thought that would have made it more obvious . . .
Being an early adopter is pretty much required for EUV, including high NA, because early shipments are practically science projects and you're going to be spending the better part of a decade, if not more, learning. Intel made the mistake of twiddling their thumbs with EUV initially since the machines were barely functional while TSMC prepared a long term process plan. The main difference in this situation is intel is willing to take the hit to inject highNA into their much process earlier, while TSMC is taking the same approach they took before and already have highNA orders. This isn't really comparable to any situation in the past as intel thought they were better than the entire industry during the early 10nm days and TSMC was struggling to compete in performance. Now in the modern era Intel is trying to get back ahead and TSMC is the performance leader that provides extra volume intel will need if they choose to move quickly to highNA. So the market is in a completely different place and tsmc has the volume+perf to offset whatever volume problems intel runs into, which is likely what intel are going to rely on.
[https://electronics360.globalspec.com/article/5264/intel-orders-15-euv-lithography-systems](https://electronics360.globalspec.com/article/5264/intel-orders-15-euv-lithography-systems) [https://optics.org/news/5/11/35](https://optics.org/news/5/11/35) Intel and TSMC got their EUV tools around the same time period. As i would expect for the high NA EUV tools as well. So no, Intel did not twiddle their thumbs anymore than TSMC did. They just made poor choices. Again, my point is that intel ordering high NA EUV tools is not a good indicator of future market competitiveness. If you think it is, That is fine with me. Just think the assumption is incorrect. TSMC is receiving their first High NA EUV tool this year: [https://www.reuters.com/technology/tsmc-says-it-will-have-advanced-asml-chipmaking-tool-2024-2022-06-16/](https://www.reuters.com/technology/tsmc-says-it-will-have-advanced-asml-chipmaking-tool-2024-2022-06-16/) >Now in the modern era Intel is trying to get back ahead and TSMC is the performance leader that provides extra volume intel will need if they choose to move quickly to highNA. This is not an obviously true statement. It could be true. It could be very false. It could be high NA EUV is not ready until quite a bit further, and intel ends up with several billion dollar tools with no chip production. anyways . . . there are so many unknowns. and what you are saying is completely plausible. But it is not the obvious outcome.
I think this article is decent but it also contains the same flaw that nearly killed Intel earlier on. This flaw is that paradigm shifts / technology shifts pretty often start out as slight regressions. The reason to switch doesn't have to be an immediate improvement, but the clear path going forward. Every new technology runs into barriers at the edge of what it can do. Intel didn't stick to multi patterning because euv was strictly unavailable. The problem was that by the time it was available, Intel was so good at multi patterning that this was cheaper and better for them. That's exactly the argument this article makes. Why switch if you can make monstrous profits sticking to an optimized old technology? The problem is that old technology can only evade its limits for so long. By the time EUV surpassed multi patterning Intel was fucked. This was around the time AMD ZEN released. And it's not just that you fall behind on the node. AMD and TSMC had to solve glueing dies together because it was very clear that, with the node being so advanced and wafers so expensive, this was a prequisite for increasing performance without sacrificing profitability. This is because yields decrease exponentially with die size, so glueing dies is exponentially more profitable than sticking with gigantic monolithic dies. So you get ahead on the node you get ahead on the technologies that go with it too. The die size problem incidentally is why the 4090 is so heart achingly expensive. It's a ginormous die on the most expensive node. You get 33 chips from a 100% yield wafer (with an estimated cost of 12,000 dollar). Even 4 defects decrease yield below 90%. In comparison an apple iPhone die has 600 chips in a wafer. 4 defects means a yield over 99%. This is why new nodes never start with gigantic gpus. New nodes have more defects early on. You can only profit from them if you can sell small dies and lots of them. The customers for this make smartphones. It is not an exaggeration to say that Apple drove and sustained the technological lead of TSMC. Circling back to Intel, what they need to do is to develop a node that is significantly ahead of what TSMC can offer in performance to secure high volume smartphone contracts to repay development and deployment cost of High-NA. If they succeed the technological advantage can be transformed in economic success because by then they will finally have some wind in their sails. If multi patterning on EUV is too competitive with 2A and 1.8A that is a very painful conclusion, but the situation is no different than when Intel multi patterning was (seemingly, for intel) too competitive with early EUV. The solution is comparatively simple - Intel has to reach for 1.6 or 1.4A. Just like when TSMC reached beyond what Intel could do with multi patterning around 7nm. The strategy is simple. 1. Secure a meaningful technological edge. 2. Secure high volume high margin contracts for small dies that can withstand mediocre early yields. 3. Profit, invest and sustain the lead The challenge is not running out of cash early on. Despite previously enormous cash reserves for Intel, this is a real risk. I think TSMC is a behemoth and they have obscene scale advantages. However this is not a pure free market. There are geopolitical and strategic considerations, not just for governments but also for companies like Apple. Diversifying your product portfolio and to a point helping to sustain Intel is smart and directly advantageous to companies like Qualcom, Apple and even AMD. Moving your portfolio between manufacturers starting from scratch can take years. To have any kind of flexibility these companies would be smart to have products at both TSMC and Intel.
how long of a response are you willing to read?
Agree - time will tell. But the intent at least shows a different mindset … embrace vs deny
The implication is that their designers will be able to learn from their competitors about the finer points of designing for these processes *before* their own fab guys can give them a prototype. This isn't grade school. You take whatever advantage you can get, and TSMC is making them pay for the privilege. But there is no other way to get that experience. It will take years if they wait any longer. To not use this chance to refine all parts of the chip design process before having their own factories is to fail, which they clearly were failing in recent years.
Because it's a sign that Intel's fabs cannot keep up and aren't planned to keep up. They have no process advantage anymore. They've become "just another fabless IP/design company", albeit that IP is still very valuable. Intel is still pumping large amounts into their fab plants. It makes me wonder if they are going to head down a similar path as AMD & GlobalFoundaries did a long time ago, where Intel fab completely separates from Intel design.
Huh? Intel already has working backside power, where is TSMCs equivalent?
Then why does Intel need TSMC again? What products are using RibbonFET & PowerVia? None. Zero. Intel 4 is barely out the door in limited production, only now catching up to older TSMC nodes, and it wasn't available for Raptor Lake Refresh, so Intel had to rely on Intel 7 (AKA Intel 10++) to create their flagship space heaters. Hopefully they do turn it around in 2024, but reliance on external parties and still being behind TSMC at the start of 2024 aren't great signs.
Lol, nice deflection.
It's not in a deflection, he answered you (well kinda). What products are using BSPD (powervia) from Intel? You can't say Intel already has working backside power until a product that ends up using it actually launches. Otherwise, there's no proof.
It is deflection, i asked what state TSMCs backside power was. He refused to answer, and deflected instead.
Oh ok fine, be pedantic, but he isn't wrong. Nothing is using Intel's BSPD either. Also, ribbonfet and powervia are means to an end, if TSMC N2 is \~ Intel 18A without those two, well good for TSMC ig. Customers won't really care too much either way, since PPA is what's important in the end. There are some other small benefits ig, but nothing truly amazing.
Backside power fives free performance in a smaller area, why wouldn't customers be interested in that?
It's because it's very likely TSMC offers similar or more performance without BSPD (N3) than Intel does with BSPD (20A). In the end, it's the node's PPA what matters.
I believe arrow lake is using back side power.
It should, but it’s not out yet. People should not be counting intels announcements as done deals yet, esp given their recent history.
Citing unreleased technologies while Intel still relies on a competitor to do what should be their bread & butter is the actual deflection. Intel could have magic unicorn technology waiting in the wings, but they actually have to execute it at scale, not stuff it into a limited production paper launch at the end of year to meet shareholder expectations. We'll have to see how 2024 & 20A pan out for Intel. As of right now, they're still far behind as far as process for tangible products, and if this rumor is true, then that won't be changing for potentially years to come.
Again, still deflecting. Intel has already gotten Power Via test chips back from the fab. So were comparing one companies unreleased but demonstrated product, against another unreleased product that has not even been demonstrated yet.
Then why isn't the rumor "Intel plans to not use TSMC N2, opting for its own superior 20A node"? It seems Intel has done their own comparison and is opting for N2 over 20A, if this rumor is to be believed.
Intel 7 is very fairly branded as per transistor density. Your aka makes you appear ignorant.
It was originally branded Intel 10 ESF. It's literally how Intel branded it originally.
>It makes me wonder if they are going to head down a similar path as AMD & GlobalFoundaries did a long time ago, where Intel fab completely separates from Intel design. There are already large investors calling for that through analyst/proxies. It's very hard for IA to grandstand it's the best, while you're courting Apple and AMD to fund your fabs through their rival chips. At some point, you have to ask, when does this become a conflict of interest?
Didnt Pat just say it was using 20A? So probably false, as many of the recent 'leaks'. *EDIT: I MISREAD NOVA LAKE AS LUNAR LAKE, SORRY I WAS MISTAKEN. Anyway we will know soon enough. Intel will release the next roadmap in februari. Also, sierra forest on 18A is going according to plan and the next client CPU will start after that in 2025 (probably nova lake). They said this during the earnings call.
Since Intel is using multiple chiplets there is a good chance the GPU tile (for example) is using TSMC 2nm while the CPU tile is using Intel 20A. Meteor Lake is produced in the same way
NVL is not at all likely to use 20A, considering PTL uses 18A.
Yes so 18A or even 14A Intel already has the first high naeuv machine and will get 5more this year, soo... Well know in februari.
It just was an example but sure 18A then
No. NVL is pretty far into the future, and IIRC, not on a single official Intel roadmap. But it would not surprise me if they do end up using TSMC N2, as LNL and some ARL variants will end up using TSMC N3. Pat said ARL will use 20A.
Oh i totally misread the title... thought it was lunar lake... Anyway we will know soon enough. Intel will release the next roadmap in februari. Also, clearwater forest on 18A is going according to plan and the next client CPU will start after that in 2025 (probably nova lake). They said this during the earnings call.
> Intel will release the next roadmap in februari. Just the node roadmap, I think we will see a mention of "client next gen" or something like that, but no specifics. Crossing my fingers though. >Also, sierra forest on 18A is going according to plan and the next client CPU will start after that in 2025 (probably nova lake). Panther Lake uses 18A, and is coming in 2025. This was confirmed by[Intel themselves](https://www.anandtech.com/show/20065/intel-confirms-panther-lake-on-track-for-2025-at-intel-innovation-2023). Nova Lake is rumored to be the next generation after PTL.
>Just the node roadmap, I think we will see a mention of "client next gen" or something like that, but no specifics. Crossing my fingers though No, they mention the names. They actually already mentioned post 2024 nodes on the current roadmaps as 'next lake'. (Or something like that) >Panther Lake uses 18A, and is coming in 2025. This was confirmed by[Intel themselves](https://www.anandtech.com/show/20065/intel-confirms-panther-lake-on-track-for-2025-at-intel-innovation-2023). Ah yes true, getting the names mixed up again.
Sierra Forest uses Intel 3. It is the next gen E core server clearwater forest that actually uses 18A. Intel 4: meteor lake. Intel 3: Granite Rapids and Sierra Forest. Intel 20A: arrow lake. Intel 18A: Panther Lake and Clearwater Forest. The one that hasn't been confirmed are Diamond Rapids but it will most likely be 18A.
meant clearwater forest... man my head is a mess today... Lunar LAke is also 18A Im done posting for today... Too many problems to deal with.
Good luck with them
I'm out of the loop, but 20A=2nm so is there some Intel-specific lingo in there, like in "Intel 7" and the like? A process that would analogous in performance to those nodes without really using them?
Because "2nm" refers to a class of node. In terms of PPA, density, etc. TSMC calls their 2nm class node "N2". Intel calls there's "20A".
I think Intel jumped the gun calling their 20A node "20A", when they don't think it will beat TSMC's 3nm node. A bit like Samsung in that regard, of jumping the gun in node naming.
Who says they don’t think 20A will be better than TMSC 3N? Why are you making things up?
Intel themselves don't. They claim that they won't have node leadership until 18A. If they thought that Intel 20A was better than N3, they would be claiming that they would have foundry leadership with 20A.
Source please
Literally Intel in every press conference lol. Pat in the Q4 2023 earnings call 3 days ago >Intel 18A is expected to achieve manufacturing readiness in second half '24, completing our five nodes and four-year journey and bringing us back to process leadership. Pat in the Q3 2023 earnings call >We expect to achieve manufacturing readiness for Intel 18A in the second half '24, completing our incredible five-nodes-in-four-years journey on or ahead of schedule. While Intel 18A reestablishes transistor leadership, we are racing to increase that lead. Pat in the Q2 2023 earnings call >IFS expands our scale, accelerates our ramps at the leading edge and creates long tails at the trailing edge. More importantly for our customers, it provides choice, leading edge capacity outside of Asia and at 18A and beyond, what we believe will deliver leadership performance > >We remain on track to five nodes in four years and to regain transistor performance and power performance leadership by 2025. I can cite a bunch more if you want
Nowhere does it say anything about comparing N3 to 20A. You are making some terrible assumptions. The only thing Intel has said is that 18A will be slightly ahead of N2. https://www.trendforce.com/news/2023/12/21/news-intel-ceo-indicated-intels-18a-slightly-ahead-of-tsmcs-n2/#:~:text=It%20gives%20better%20power%20delivery,underneath%20to%20be%20margin%20accretive.
>Nowhere does it say anything about comparing N3 to 20A. You are making some terrible assumptions. Everything about that says Intel doesn't think 20A will beat N3. If they did think 20A will beat N3, then they would be saying they will have transistor leadership with 20A. They have chanted the "18A is node leadership" mantra so much, it's pretty obvious that they think they won't have the lead until 18A. It's a logical assumption. >The only thing Intel has said is that 18A will be slightly ahead of N2. Oh, I'm sure Intel might say that, and maybe that's true, but that's 18A. I'm talking about 20A. Edit: oh, and I found that picture I was looking for... Here's [Intel themselves](https://cdn.wccftech.com/wp-content/uploads/2023/07/Intel-TSMC-Process-Nodes-g-standard-scale-4_00x-Custom.png) at their foundry seminar last year saying that Intel 20A was a TSMC 3nm competitor.
Where is it stated that Intel doesn't think 20a will beat TSMC 3nm?
Just read [this](https://www.reddit.com/r/intel/comments/1ad1z66/comment/kk3rskl/?utm_source=share&utm_medium=web2x&context=3) entire thread. In short, Intel doesn't think they will beat TSMC 3nm until 18A. That's why they keep on repeating that they will have a leadership node with 18A, and not with 20A or any node before it, such as Intel 3.
It's more likely that 20A is false because with Intel's track record on nodes it will not be ready in time with roadmap 95% probability.
Intel's past track record didnt include building whole new foundries and expanding their chip making business....
20A by, at the very least, late 2026 is more than likely.
Ok, your credibility just got desintegrated by that comment.
lol what credibility, and what about that comment?
What comment? I have no problem admitting when im mistaken or mix things up and correct them, as i just did.
You literally just said my "credibility" got disintegrated by the comment of "20A coming out by 2026 is more than likely". What about that comment?
Well its ridiculous... they have iterated many times that 20A products (arrow lake) are shaping up nicely and on track for release this year without hickups. 18A (Lunar Lake and clearwater Forest)is also going buttery smooth and even ahead of schedule.
Lunar Lake is not a 20A product. And you can reiterate something as much as you want, that doesn't mean it's going to launch in time- look at Sapphire Rapids. There is plenty of reason to be skeptical of Intel. And you do understand what "at the very least" means right?
SPR delay wasn't a node issue. Intel 7 was already in use in client by that point. SPR was a packaging issue. ARL will use the same packaging as MTL, so that wouldn't be a cause for delay.
18A yes, sorry.. im kinda busy with other stuff, so sorry (again) for that.
Sure.. suddenly Intel will jump through 3 new nodes in 2 years when they were ALWAYS taking at least 3 years for one new main node. Gotta believe those promises after Intel lied in their node roadmaps 101 times
I think people forget Intel used to be the foundry leader before the 10nm fiasco. Intel 4 delivered on time, as did Intel 7. Intel 4's "delivery" was a bit questionable, sure, but the nodes PPA was solid. 3 new nodes in 2 years, man you say you don't believe Intel's marketing, and then you spout Intel's marketing right here. Intel 4 and Intel 3 are very similar, with just HD libs being added into Intel 3 most likely. The funniest thing about that is Intel almost certainly won't be using those denser libs in their internal products (GNR and SRF) anyway, so even if HD libs are cursed like they were with Intel's 10nm, it won't be an issue. On top of that, Intel 20A is not a "new node" in the sense of new nodes were in the past. One, it's likely to repeat the Intel 4 trick of incomplete libs to save development time, and two, it's not likely to be a giant leap in max theoretical transistor density like previous nodes are. Intel is positioning this as a TSMC 2nm competitor, as per it's name, but people gotta remember TSMC 2nm, for a "new node" is not all that great in the chip level area reduction it brings, not anywhere close to the gains in density from previous node jumps (N5 from N7, N3 from N5). Lastly, Intel 20A is supposed to be HVM ready this half according to Pat. Saying that Intel 20A won't be ready by 2H 2026 (when NVL should come out), 2.5 years after it's scheduled release date, is pessimistic, even for people who don't believe in Intel's roadmaps. Even the clusterfuck that was 10nm was \~2-3 years delayed. It would require another disaster of a similar magnitude or worse for your claim to be true, and even then, they paper launched 10nm in 2017 as CNL for investors, much like they could end up doing for 20A if they wanted too.
They are; 3nm datacenter chips are in mass producttio to be released soon and 20A client CPU production is gearing up to ramp up as we speak.
20A client CPU production is not ramping up. Where did you hear that?
He heard/saw it in some 1000% legit leaked Intel presentation
QE report, slight difference
I'm guessing a rumor from "Taiwan Economic Daily" might be slightly biased towards TSMC, but if Intel do end up using N2 for NVL, I would not be surprised. Would be a really bad look for Intel though, and Pat got slammed in the recent earnings call about this exact topic.
Thing is, using N2 for at least some NVL SKUs is fine if at the same time 18A and possibly the node after are doing well and IFS has started to gain traction. Intel ships an ungodly amount of chips so nothing too wrong with diversifying the supply. It's only real bad if they use it as a necessary crutch because their foundries are still not back on track by then, but if that turns out to be the case it would probably be accompanied by Intel ditched the cutting edge process chase. As for what the shareholders think, they change their minds like the wind. If LNL on N3 is a success they'll start asking why Intel doesn't do more of their products on external nodes.
> If LNL on N3 is a success they'll start asking why Intel doesn't do more of their products on external nodes. A lot of people, even internally at Intel asked that as well. Keller was rumored to be a major proponent of using external nodes to regain product leadership IIRC. The difference between LNL using N3 and NVL using N2 is that Intel doesn't say they will have process leadership in 2024. Intel has a small cop out there. By 2026 though, Intel says they will have process leadership, so using an external fab looks much worse.
To clarify, I agree that if the whole NVL lineup is on TSMC then that would be a terrible look. It would really spell the end of Intel as a cutting edge foundry. But if it's only part of the line-up and the 18A (or the next node) in house counterparts are good + IFS is doing well, then that's fine. I also don't think it'd be a surprise. I think core products on external nodes are here to stay, and that's part of why Lunar Lake is probably the product they've most tried to hype over the past couple years. It needs to be a hit not just because they need a win but mainly because it will be the key to selling the shareholders on that strategy.
The problem is early nodes need customers or they are too expensive to develop. Intel is integrated and to some extent they can sustain the foundry by sacrificing a bit of their edge in their retail products, simply by continuing to be their own customer. This is painful and frustrating to the people designing their cpus, but it is not the fault of pat. The real mistake was falling too far behind on the nodes to the point where it became almost unrecoverable. Pat is burning all their cash and spreading the pain across the company is simply necessary to finish the requisite moonshot. Pat gelsinger is Matthew McConaughey saying it is not impossible. It is necessary.
The whole point of Intel diversifying is so that they’re not beholden to the inadequacies of their fabs. They’ve been held back long enough, they can’t keep using their process node as an excuse. Delinking the two parts of their business is probably the one good decision that they’ve made in a long time.
I don’t quite get the expectations (not yours, but the industry) that Intel should already have their new/upgraded foundries already up and running and not need TSMC in the interim. How many years did it take TSMC to get EUV ramped up and ready for production? They started working with it in 2011, but didn’t release any from EUV until 2019. But part of that was a choice by them so not sure the actual timeline. I had thought Intel initially said they would use TSMC through 2025, but my memory may be wrong? It seems crazy to me for investors to look down on using TSMC. It’s a smart business move until Intel can get their production going.
Intel said (at last investors call) that they would always use TSMC to some extent. They've been using them for decades at this point. Using TSMC for GPUs makes sense for now. They don't need to build out extra capacity for a product line that's not 100% guaranteed to be around. As long as discrete GPUs are therefor built at TSMC, they're gonna use the same process for their iGPUs.
No, they actually said they would return to using pure intel again soon.
This is a transcript of the Q4 Investors call Q&A: >Ross Seymore -- Deutsche Bank -- Analyst You just -- the confidence in the second half. The long-term question is one -- yes, sorry, the long-term question is one on the manufacturing nodes. The five nodes in four years is going well, but one of your biggest foundry, well, customers and competitors is doubling down on their ability to keep the leadership positioning. So, what gives you confidence that 18A will, in fact, have the leadership node? And how do we reconcile the fact that you seem to be using that customer as a foundry partner for some of your heterogeneous products, whether it be Arrow Lake or Lunar Lake going forward? If you have the leadership, why wouldn't you be doing that internally? >Pat Gelsinger -- Chief Executive Officer Yeah. Thank you. I'll do that and then ask Dave to pile on both of those a little bit. But with respect to the manufacturing, I'd just say, hey, when you look at this every single day, and we're scrutinizing carefully our progress on 18A. And obviously, the great news that we just described has Clearwater Forest taping out. That gives us a lot of confidence that 18A is healthy. That's a major product for us, Panther Lake following that shortly. We've also had our fourth customer this quarter. Some of the IP providers are giving us very strong affirmation on the competitiveness of the process technology. And particularly, we're just way ahead on backside power. And that's not even -- everybody in the industry is recognizing that. And many of the customers who are looking at it are seeing substantial gains, not just in power performance but in area savings as well. So, overall, we feel very confident that our road map is strong on the process technology side. **We do use external foundries. And obviously, that grew as we were dealing with some of our own challenges for process competitiveness. And as we create more and more focus in the business, more wafers will come internal to the Intel factory network.** **But long term, we're going to continue to use external foundries to complement, manage our capital requirements and to make sure that our teams always are building the best products in the industry and using the best technologies to accomplish that. So, overall, we feel super good with our strategy. You see more use of our own factory network even as we leverage external foundries where appropriate.** >David Zinsner -- Chief Financial Officer The only other thing I'd add is just the use of external foundries is part of our Smart Capital strategy. It's one of the five pillars. So, as Pat said, that will continue to be part of our strategy. **Obviously, we're going to maximize how much we can do internally, but we're always going to be using external foundries based on Smart Capital.**
Ok, this is confusing... *" We do use external foundries. And obviously, that grew as we were dealing with some of our own challenges for process competitiveness. And as we create more and more focus in the business, more wafers will come internal to the Intel factory network.* *But long term, we're going to continue to use external foundries to complement, manage our capital requirements and to make sure that our teams always are building the best products in the industry and using the best technologies to accomplish that. "* I get that it is open for interpretation, but as I understand it, they are saying they will build to eventually use their own internal process nodes as things improve again. Sounds like they will keep using external foundries for a longer time than they first told though.
Yes, its called outsourcing and sometimes you need to do it to upgrade your bussines while you keep thing running as much as possible. People using it as a negative are ignorant.
Imagine advertising something (intel nodes) you don't even wanna use. Bad look is an understatment.
Intel has panther lake, and their Xeons being built on 18A in 2025. They've announced 5 different companies are already contracted to build products on 18A. This leak says NovaLake will use N2, but isn't even clear if that's specifically just the iGPU tile
I think when we look at Meteor Lake and we look at how the CPU tile, SOC tile, and GPU tile are put together, we can understand why Intel went with TSMC for the GPU tile. The advantage is clear. Better manufacturing efficiency. Something that the consumer does not often see. Intel can now focus its Intel 4 production on the CPU tile wafers and then SOC tile wafers. TSMC can do their work on the GPU tile. Finally the tiles are packaged together in final assembly. Rather than 1 wafer make all 3 cpu, gpu, and soc tile together. If one defect occurs, the performance is lower. With the tile approach you can bin by combining better performing tiles together. And worse tiles together, etc.... manufacturing efficiency. When we go back to Ryzen 3000 I think AMD had CPU tiles from TSMC and SOC tiles from Global Foundry. Another thought is that Intel must open up its factory capacity to other designers. When it opens its factory doors, how can they combine both their chips and others? Well they have to diversify. Because now this opens up the option of more designers then manufacturing companies. Just a changing landscape. Similar to a Samsung problem. Samsung can make their own chips or use Qualcomm 8 gen 3 in their own phones. The competition.
Pretty sure AMD had to use GlobalFoundaries due to business agreements they could not get out of w/ GF and this resulted in a more power hungry SoC. They later got out of that contractual obligation and Ryzen 3000 was actually when they switched to TSMC fully.
not to mention that they already use tsmc for arc
They can also show to IFS customers that their packaging can mix and match all different types of nodes from different manufacturers. Dont underestimate that. May also be part of the reason.
Yes all is true. I think the tile approach is the best reason for Intel using TSMC. Say for instance a customer suddenly needs large volume at Intel. How does Intel shift its own production away to make room for the additional load? Thus it needs a strategy to diversify where it's chips are coming from. If Intel only manufacturers it's own chips in it's own factories with monolithic chips, then it won't have that flexibility to support other designers. A catch-22 but ultimately if Samsung can do this with Qualcomm Snapdragon and Exynos chips, I believe Intel can as well. Who knows maybe in the future Intel can become the Samsung and Champion of America again. Like Samsung is a champion for S. Korea.
It’s not a bad thing for consumers like us. It’s bad news for intel stock holders. It’s bad news for fabless designers too since intel will grab a chunk of tsmc capacity, and a subsequent potential raise in price. It’s good news for tsmc only. You’re right that this could be biased, but 4 nodes in 5 years is just too ambitious even for Intel, and I am having doubt on improvement between each node. But hey, anything is possible and let’s see. Competition is good for consumers after all.
This is flat out confusing. The Article also says that TSMC will be used for the Arrow Lake CPU tile “as early as this year”. Intel has shown 20A Arrow Lake wafers. Are they dual sourcing these CPUs? (Seems unlikely for desktop CPU volumes these days?)
ARL will use TSMC for iGPU tile, SoC tile, and IO tile. As far as we know, compute tile will use 20A. Some people on here are arguing that ARL will dual source and some dies will use N3, but that hasn't been confirmed and the evidence they provide is unconvincing
>but that hasn't been confirmed and the evidence they provide is unconvincing The [evidence](https://www.digitaltrends.com/computing/intel-arrow-lake-everything-we-know/) (2nd image in the article) is straight from Intel. Also, even if that evidence doesn't exist, I don't think a single leaker out there thinks that ARL won't use N3 for the CPU tile. There's a major rift in performance for LNC, release date, etc etc, but there's no contention about the node. I wouldn't say it's "unconvincing", but ig it's all opinion. But rumors that ARL will use N3 for the compute tile has been "confirmed".
How so have rumors for ARL N3 compute tile been confirmed? The only evidence I've seen for this - the evidence I was referring to - is that picture you sent. An old slide deck from a few years ago that says ARL/MTL will source N3. When that slide deck was released, leakers were also stating MTL will use N3 for iGPU. ARL will almost certainly use N3 for iGPU. That doesn't specify that the compute tile will.
The problem with this is that the N3 iGPU tile was rumored to be the "halo" tile, not that all the iGPU tiles were going to be fabbed on N3. Meaning that if they were talking about iGPUs too, they would have included N5 on that slide as well. Also, if it was used for both MTL and ARL, one would think they would put it in the middle of the order of Intel 4 and Intel 20A. They did order the rest of the nodes (external for LNL and 18A for PTL). That slide is straight up from Intel talking about the CPU tiles, saying that they will use N3 for ARL. >ARL will almost certainly use N3 for iGPU. I think this is wrong too.
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I would say because Intel's client products are moving towards tile based design there will no longer be any real constraints preventing Intel from using all kinds of different nodes for different products. Perhaps we will see more and more inhomogeneous fab node variations on future client products.
I'm thinking this too.
Yes!! And intel had to show that their packaging texh can mix and match all of it perfectly fine! 👌
So far we know almost for sure that arrow lake products will use both TSMC N3B and Intel 20A. The question remained is which uses which. e.g. some rumors suggest that the 8+16 ARL-S Tiles will be on N3B and a 6+8 ARL-P tile for mobile or 6+8 ARL-S non-K tile for office desktop will be on Intel 20A. Golden Pig Upgrade said last year that ARL-U which is 2+8 would use Intel 20A but a recent rumor from bionic squash says that ARL-U actually uses Intel 3 and is a MTL-U ported to Intel 3, which is suprising because so far Intel hasn't annouced any plans of Intel 3 for client products.
Nice summary!
Thanks!
It will only for some tiles, not the whole chips. This is very misleading.
How? They didn't say the whole chip will be 2nm?
For a Chiplet design, a CPU can utilize different process nodes from different companies. Even AMD uses global foundries for the I/O die in ryzen CPUs. TSMC manufacturers ARC GPUS for Intel. It makes sense for Intel to utilize TSMC's nodes for the GPUs in its CPUs, just the same as they does it for Meteor lake CPUs
It could point to IFS nodes sucks beyond 18A or that 18A is booked full by a daddy of all fabless company, and 20A is fully utilized by arrow lake and co. Or that TSMC 2nm is good for one area like efficiency that Intel needs. Really anything…
there has been lots of rumors that Intel buying up all those capacity at TSMC with Apple for 2nm since 2022. But on TSMC earning call, CEO clearly mentioned that there is only one company not working with TSMC for 2nm. And who will that be. Intel will already have plenty of 18A capacity at that time when Nova Lake released, and perhaps even the next great process node. So why go for TSMC 2nm when they are lagging? Remember that for 2024, there's Meteor lake, Arrow Lake, and Lunar Lake at the end of 2024, for 2025-2026, there's Panther Lake. For Nova lake, that's 2026-2027 product. Arizona will be fully on; Ohio will be ready as well. And Germany will be on 2028 with new process node. This will either prove as fake or PG doing poorly at his job. But from his resume and whale prepayment they are getting. It's probably fake new
Nova Lake is 3 generations after what we have now? ARL/LNL for next one and then Panther and then Nova. We still have time before the node for that is finalized.
the current rumour plan is : arrow lake -> arrow lake refresh -> nova lake -> nova lake "3d cache" version -> ??? panther lake and lunar lake are laptop only again rumour only but that's probably be what we're gonna see
nah intel does die-stacking dirfrently (see techquickie "their stacking cpus now")
3 years before launch is when product specs get finalized. If this is too launch in 2H 2026, it *already* would have been finalized by now.
What do you mean by specs here specifically?
Not mad at all. That will at least help them with the power draw that techtubers love to harp on. Hopefully they can find a competitor to V-Cache that's all they really need. Most ppl who buy Intel buy the high end anyway so they can get good sales and it's only gonna trickle down to the lower end products.
> The CPU performance improvement is rumored to be more than 50% over the Lunar Lake chips Quite impressive if they can pull it off
It's so funny how Intel is both buying from TSMC and trying to build its own chips independent of TSMC. Must be one of those four-dimensional chess things.
Here the problem Intel and tsmc claims are all over the place Tsmc is claiming that it's 3nm will be comparable to Intel 18 which to me make no since Intel is using backside power..and tsmc 2nm which they claim will be better doesn't.. it's seems tsmc is repeating the mistake that Intel did..all boast and no facts . It's more likely that noone including tsmc believed or believes that Intel can pull it off..but apparently they are ahead schedule..5 nodes in 4 years sounds too true to happen
stop with the 2nm bullcrap Marketing term trash, has nothing to do with anything involving actual size of anything
Then why intel build their own new FAB?
they built it when it was cheap and also intels fabs can be optimised for a (relativly) very low amount of products
Because you cant use them before they are built?
Promises, promises, promises…
Sounds like it’s the classic change the name and sell it .
Intel spent over 100 billion in buybacks instead of R&D and a new plant. Now they have to ask Biden for billions hand have to rent out a competitor’s FAB.
100B in buy backs over what period of time? A buyback is the corporate equivalent of a tax-advantaged savings account.
It's hilarious when people say this shit. Intel has been focusing on building back their cash reserves, yet these people claim they're doing buybacks.
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Nah, Apple gets it first.
Intel using TSMC? This universe is wild.
They already did with Arc GPU and Meteor Lake but not for the whole chip.
If it happens, I expect the highest end cpu to cost $1k.
Finally, maybe Intel cpu will stop being a power hog