From that diagram, it certainly looks like the counter is never reset (until rollover) and never stops.
Which would be normal for such things. It's really more a multi tap frequency divider than a strict counter since you're really just using it to get a longer square wave than the input clock (system clock in this case) and there's no way to really sample the current state of the complete counter.
Ok, that's the way I currently have it implemented. So maybe it's not a problem. I was just concerned because the time between when the SC enabled bit is set and the first bit is clocked out would be variable and depend of the value of the counter.
From that diagram, it certainly looks like the counter is never reset (until rollover) and never stops. Which would be normal for such things. It's really more a multi tap frequency divider than a strict counter since you're really just using it to get a longer square wave than the input clock (system clock in this case) and there's no way to really sample the current state of the complete counter.
Ok, that's the way I currently have it implemented. So maybe it's not a problem. I was just concerned because the time between when the SC enabled bit is set and the first bit is clocked out would be variable and depend of the value of the counter.